Many industries developing FPGA based electronic products choose to carry out inadequate or almost no simulation verification while resorting to only performing ad-hoc lab testing for debugging, verification and integration testing. Some of the common given reasons for this attitude towards simulation are, “there is no budget allocated in the project for simulation verification”, “there is …
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FPGA Design Fundas 0.2: The Need For Simulation Verification & Integration Testing
Many industries developing FPGA based electronic products choose to carry out inadequate or almost no simulation verification while resorting to only performing ad-hoc lab testing for debugging, verification and integration testing. Some of the common given reasons for this attitude towards simulation are, “there is no budget allocated in the project for simulation verification”, “there is …
Continue reading FPGA Design Fundas 0.2: The Need For Simulation Verification & Integration Testing
Universal FPGA Testing Methodology (UFTM™)
Universal FPGA Testing Methodology (UFTM™) is largely based on the principles of the world renowned, industry standard, Universal Verification Methodology (UVM). UVM is used and applied to functionally verify digital logic designs implemented using Hardware Description Languages (HDL) like VHDL, Verilog, System Verilog in simulation. UVM and UVM System Verilog class libraries are used in …
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Capturing Activity in ILA at Design Reset/Start-up Time in Xilinx Vivado
I know that we would like to know how to capture activity in the implemented logic at reset time. The default simple trigger capture in Vivado Logic Analyzer is manual in which case it is impossible to capture such activity. However the following steps will enable you to add an automatic trigger at reset just …
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Problem with Cross Compiling OpenCV Application for Xilinx Zynq – ARM on Ubuntu Linux OS
Problem: When cross compiling an OpenCV-2.4.9 application for the Zynq – ARM using a Makefile on Ubuntu 14.04, it generated the following error: “make: Circular Makefile.out <- Makefile dependency dropped” I could not understand what caused it and the solutions found on web pointed towards some sort of circular dependencies. I checked and rechecked again …
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DIY Hand Soldered SMD PCB with FPGA – Papilio Duo
Assembled the Paplio Duo board by completely hand soldering and it works! Could not have done it without the help and guidance of my fellow makers at RLAB. So proud to be able to successfully solder the Xilinx Spartan 6 FPGA on this board :). Website for this Open Source board is at Gadget Factory .
Cross Compiling OpenCV for Xilinx Zynq Arm on Ubuntu Linux OS
I am writing this to keep a log for myself and others whenever I want to cross compile OpenCV for Xilinx Zynq – ARM platform for Ubuntu 14.04. I have followed instructions mentioned on Xilinx-Wiki however I had to tweak quite a few instructions for me at a few places in order to successfully compile OpenCV. I …
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