Category:FPGA

FPGA Design Fundas 0.5: Ignoring FPGA Synthesis Tool Warnings

Posted on Updated on by edgesmart.techCategories:Altera, AMD, ASIC, Circuit, CMOS, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, HDL, VHDL, Xilinx

What are your thoughts on ignoring tool warnings generated by FPGA synthesis tools like Vivado? I have come across clients, from one end of spectrum, in the name of prototype development, opted to completely ignore all warnings generated by the tool, to the other end of spectrum where I helped develop a comprehensive log parser …
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FPGA Design Fundas 0.4: Vivado Revision Control & Automation

Posted on Updated on by edgesmart.techCategories:Altera, AMD, ASIC, Circuit, CMOS, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, HDL, Revision Control, RTL, Source Control, SystemVerilog, Verilog, Version Control, VHDL, Xilinx

Lets tackle the bull by its horns! So what is a revision control? It is fundamentally a method to keep track of source file changes, such that one can revert to a certain point in the past, combine multiple source changes into a release, fork into a design with different features, aid conflict resolution and …
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FPGA Design Fundas 0.2: The Need For Simulation Verification & Integration Testing

Posted on Updated on by edgesmart.techCategories:ASIC, Debug, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, Modelsim, Simulation, Simulation, Testing, Verification

Many industries developing FPGA based electronic products choose to carry out inadequate or almost no simulation verification while resorting to only performing ad-hoc lab testing for debugging, verification and integration testing. Some of the common given reasons for this attitude towards simulation are, “there is no budget allocated in the project for simulation verification”, “there is …
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FPGA Design Fundas 0.1: ASIC vs FPGA

Posted on Updated on by edgesmart.techCategories:Altera, ASIC, Circuit, CMOS, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, HDL, RTL, VHDL

There are many difference between an ASIC and FPGA however, this article attempts to explain the fundamental difference between an Application Specific Integrated Circuit (ASIC) and a Field Programmable Gate Array (FPGA). Some basic understanding of digital logic design or boolean logic is required. Let us take an example of the AND gate from the …
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FPGA Design Fundas 0: VHDL Is Not A Programming Language!

Posted on Updated on by edgesmart.techCategories:Altera, ASIC, Circuit, CMOS, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, HDL, HVL, RTL, VHDL

Verilog is not a programming language! SystemVerilog is not a programming language! (Here programming language means conventional software which typically executes on a processor.) VHDL, Verilog and SystemVerilog languages are referred to as Hardware Description Languages (HDLs). HDL is a textual description of hardware (i.e. a digital logic circuit). HDL syntax includes textual description definitions …
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Universal FPGA Testing Methodology (UFTM™)

Posted on Updated on by edgesmart.techCategories:FPGA, Testing, Verification

Universal FPGA Testing Methodology (UFTM™) is largely based on the principles of the world renowned, industry standard, Universal Verification Methodology (UVM). UVM is used and applied to functionally verify digital logic designs implemented using Hardware Description Languages (HDL) like VHDL, Verilog, System Verilog in simulation. UVM and UVM System Verilog class libraries are used in …
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