What are your thoughts on ignoring tool warnings generated by FPGA synthesis tools like Vivado? I have come across clients, from one end of spectrum, in the name of prototype development, opted to completely ignore all warnings generated by the tool, to the other end of spectrum where I helped develop a comprehensive log parser …
Continue reading FPGA Design Fundas 0.5: Ignoring FPGA Synthesis Tool Warnings
Author:edgesmart.tech
FPGA Design Fundas 0.4: Vivado Revision Control & Automation
Lets tackle the bull by its horns! So what is a revision control? It is fundamentally a method to keep track of source file changes, such that one can revert to a certain point in the past, combine multiple source changes into a release, fork into a design with different features, aid conflict resolution and …
Continue reading FPGA Design Fundas 0.4: Vivado Revision Control & Automation
Custom FPGA Board DDR2-SODIMM DQ & DQS Swap Issue
While working on a European Research project called FASTMATCH where the project demonstration was carried out by implementing and intelligent high-speed Intrusion Detection System (IDS). The demonstrator platform was a custom developed 14 layer electronic circuit board comprising of two Xilinx Virtex-5 FPGAs performing real-time line-rate string matching at 10Gbps. During our development, we noticed …
Continue reading Custom FPGA Board DDR2-SODIMM DQ & DQS Swap Issue
FPGA Design Fundas 0.3: The Real Cost of Skipping Simulation Verification!
Many industries developing FPGA based electronic products choose to carry out inadequate or almost no simulation verification while resorting to only performing ad-hoc lab testing for debugging, verification and integration testing. Some of the common given reasons for this attitude towards simulation are, “there is no budget allocated in the project for simulation verification”, “there is …
Continue reading FPGA Design Fundas 0.3: The Real Cost of Skipping Simulation Verification!
FPGA Design Fundas 0.2: The Need For Simulation Verification & Integration Testing
Many industries developing FPGA based electronic products choose to carry out inadequate or almost no simulation verification while resorting to only performing ad-hoc lab testing for debugging, verification and integration testing. Some of the common given reasons for this attitude towards simulation are, “there is no budget allocated in the project for simulation verification”, “there is …
Continue reading FPGA Design Fundas 0.2: The Need For Simulation Verification & Integration Testing
FPGA Design Fundas 0.1: ASIC vs FPGA
There are many difference between an ASIC and FPGA however, this article attempts to explain the fundamental difference between an Application Specific Integrated Circuit (ASIC) and a Field Programmable Gate Array (FPGA). Some basic understanding of digital logic design or boolean logic is required. Let us take an example of the AND gate from the …
Continue reading FPGA Design Fundas 0.1: ASIC vs FPGA
FPGA Design Fundas 0: VHDL Is Not A Programming Language!
Verilog is not a programming language! SystemVerilog is not a programming language! (Here programming language means conventional software which typically executes on a processor.) VHDL, Verilog and SystemVerilog languages are referred to as Hardware Description Languages (HDLs). HDL is a textual description of hardware (i.e. a digital logic circuit). HDL syntax includes textual description definitions …
Continue reading FPGA Design Fundas 0: VHDL Is Not A Programming Language!
Universal FPGA Testing Methodology (UFTM™)
Universal FPGA Testing Methodology (UFTM™) is largely based on the principles of the world renowned, industry standard, Universal Verification Methodology (UVM). UVM is used and applied to functionally verify digital logic designs implemented using Hardware Description Languages (HDL) like VHDL, Verilog, System Verilog in simulation. UVM and UVM System Verilog class libraries are used in …
Continue reading Universal FPGA Testing Methodology (UFTM™)
Capturing Activity in ILA at Design Reset/Start-up Time in Xilinx Vivado
I know that we would like to know how to capture activity in the implemented logic at reset time. The default simple trigger capture in Vivado Logic Analyzer is manual in which case it is impossible to capture such activity. However the following steps will enable you to add an automatic trigger at reset just …
Continue reading Capturing Activity in ILA at Design Reset/Start-up Time in Xilinx Vivado
Problem with Cross Compiling OpenCV Application for Xilinx Zynq – ARM on Ubuntu Linux OS
Problem: When cross compiling an OpenCV-2.4.9 application for the Zynq – ARM using a Makefile on Ubuntu 14.04, it generated the following error: “make: Circular Makefile.out <- Makefile dependency dropped” I could not understand what caused it and the solutions found on web pointed towards some sort of circular dependencies. I checked and rechecked again …
Continue reading Problem with Cross Compiling OpenCV Application for Xilinx Zynq – ARM on Ubuntu Linux OS