Category:RTL

FPGA Design Fundas 0.4: Vivado Revision Control & Automation

Posted on Updated on by edgesmart.techCategories:Altera, AMD, ASIC, Circuit, CMOS, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, HDL, Revision Control, RTL, Source Control, SystemVerilog, Verilog, Version Control, VHDL, Xilinx

Lets tackle the bull by its horns! So what is a revision control? It is fundamentally a method to keep track of source file changes, such that one can revert to a certain point in the past, combine multiple source changes into a release, fork into a design with different features, aid conflict resolution and …
Continue reading FPGA Design Fundas 0.4: Vivado Revision Control & Automation

FPGA Design Fundas 0.1: ASIC vs FPGA

Posted on Updated on by edgesmart.techCategories:Altera, ASIC, Circuit, CMOS, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, HDL, RTL, VHDL

There are many difference between an ASIC and FPGA however, this article attempts to explain the fundamental difference between an Application Specific Integrated Circuit (ASIC) and a Field Programmable Gate Array (FPGA). Some basic understanding of digital logic design or boolean logic is required. Let us take an example of the AND gate from the …
Continue reading FPGA Design Fundas 0.1: ASIC vs FPGA

FPGA Design Fundas 0: VHDL Is Not A Programming Language!

Posted on Updated on by edgesmart.techCategories:Altera, ASIC, Circuit, CMOS, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, HDL, HVL, RTL, VHDL

Verilog is not a programming language! SystemVerilog is not a programming language! (Here programming language means conventional software which typically executes on a processor.) VHDL, Verilog and SystemVerilog languages are referred to as Hardware Description Languages (HDLs). HDL is a textual description of hardware (i.e. a digital logic circuit). HDL syntax includes textual description definitions …
Continue reading FPGA Design Fundas 0: VHDL Is Not A Programming Language!