Category:Xilinx

FPGA Design Fundas 0.5: Ignoring FPGA Synthesis Tool Warnings

Posted on Updated on by edgesmart.techCategories:Altera, AMD, ASIC, Circuit, CMOS, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, HDL, VHDL, Xilinx

What are your thoughts on ignoring tool warnings generated by FPGA synthesis tools like Vivado? I have come across clients, from one end of spectrum, in the name of prototype development, opted to completely ignore all warnings generated by the tool, to the other end of spectrum where I helped develop a comprehensive log parser …
Continue reading FPGA Design Fundas 0.5: Ignoring FPGA Synthesis Tool Warnings

FPGA Design Fundas 0.4: Vivado Revision Control & Automation

Posted on Updated on by edgesmart.techCategories:Altera, AMD, ASIC, Circuit, CMOS, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, HDL, Revision Control, RTL, Source Control, SystemVerilog, Verilog, Version Control, VHDL, Xilinx

Lets tackle the bull by its horns! So what is a revision control? It is fundamentally a method to keep track of source file changes, such that one can revert to a certain point in the past, combine multiple source changes into a release, fork into a design with different features, aid conflict resolution and …
Continue reading FPGA Design Fundas 0.4: Vivado Revision Control & Automation