Many industries developing FPGA based electronic products choose to carry out inadequate or almost no simulation verification while resorting to only performing ad-hoc lab testing for debugging, verification and integration testing. Some of the common given reasons for this attitude towards simulation are, “there is no budget allocated in the project for simulation verification”, “there is …
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Category:Debug
Capturing Activity in ILA at Design Reset/Start-up Time in Xilinx Vivado
I know that we would like to know how to capture activity in the implemented logic at reset time. The default simple trigger capture in Vivado Logic Analyzer is manual in which case it is impossible to capture such activity. However the following steps will enable you to add an automatic trigger at reset just …
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