Category:Altera

FPGA Design Fundas 0.5: Ignoring FPGA Synthesis Tool Warnings

Posted on Updated on by edgesmart.techCategories:Altera, AMD, ASIC, Circuit, CMOS, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, HDL, VHDL, Xilinx

What are your thoughts on ignoring tool warnings generated by FPGA synthesis tools like Vivado? I have come across clients, from one end of spectrum, in the name of prototype development, opted to completely ignore all warnings generated by the tool, to the other end of spectrum where I helped develop a comprehensive log parser …
Continue reading FPGA Design Fundas 0.5: Ignoring FPGA Synthesis Tool Warnings

FPGA Design Fundas 0.4: Vivado Revision Control & Automation

Posted on Updated on by edgesmart.techCategories:Altera, AMD, ASIC, Circuit, CMOS, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, HDL, Revision Control, RTL, Source Control, SystemVerilog, Verilog, Version Control, VHDL, Xilinx

Lets tackle the bull by its horns! So what is a revision control? It is fundamentally a method to keep track of source file changes, such that one can revert to a certain point in the past, combine multiple source changes into a release, fork into a design with different features, aid conflict resolution and …
Continue reading FPGA Design Fundas 0.4: Vivado Revision Control & Automation

FPGA Design Fundas 0.1: ASIC vs FPGA

Posted on Updated on by edgesmart.techCategories:Altera, ASIC, Circuit, CMOS, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, HDL, RTL, VHDL

There are many difference between an ASIC and FPGA however, this article attempts to explain the fundamental difference between an Application Specific Integrated Circuit (ASIC) and a Field Programmable Gate Array (FPGA). Some basic understanding of digital logic design or boolean logic is required. Let us take an example of the AND gate from the …
Continue reading FPGA Design Fundas 0.1: ASIC vs FPGA

FPGA Design Fundas 0: VHDL Is Not A Programming Language!

Posted on Updated on by edgesmart.techCategories:Altera, ASIC, Circuit, CMOS, DIGITAL, Digital Logic, Digital Logic Circuit, FPGA, HDL, HVL, RTL, VHDL

Verilog is not a programming language! SystemVerilog is not a programming language! (Here programming language means conventional software which typically executes on a processor.) VHDL, Verilog and SystemVerilog languages are referred to as Hardware Description Languages (HDLs). HDL is a textual description of hardware (i.e. a digital logic circuit). HDL syntax includes textual description definitions …
Continue reading FPGA Design Fundas 0: VHDL Is Not A Programming Language!

Installing Altera Modelsim on 64-bit Ubuntu 14.04 – Linux

Posted on Updated on by edgesmart.techCategories:Altera, Installation, Intel, Linux, Modelsim, Ubuntu

I downloaded and the ModelSim-Altera Starter Edition for Linux from Altera (now part of Intel) website at the following webpage: http://dl.altera.com/?product=modelsim_ae#tabs-2 I then installed it on the 64-bit Ubuntu-14.04. After which I ran the following command from within the bin directory of the installed Modelsim and despite the executable present I got the following error: command$> …
Continue reading Installing Altera Modelsim on 64-bit Ubuntu 14.04 – Linux