What are your thoughts on ignoring tool warnings generated by FPGA synthesis tools like Vivado?
I have come across clients, from one end of spectrum, in the name of prototype development, opted to completely ignore all warnings generated by the tool, to the other end of spectrum where I helped develop a comprehensive log parser that classified the warnings as per the requirements of the project and company.
I do understand that fixing warnings is a cost however, I believe ignoring the warnings almost always ends up being costlier.
For example, in a start-up situation, say the company is required to demonstrate something as quickly as possible in order to survive, however, does this reason justify ignoring the tool warnings totally and trying to get something working by brute force. I personally do not believe this approach does any good at all.
1) What happens when the investors say, this is all good, now go and develop a stable sellable product? By that time, the RTL source has become so messy and the warnings count end up in thousands.
2) How does one even begin to contemplate cleaning up such mess?
3) How does one even begin to contemplate prioritising the thousands of tool reported issues? Many “FPGA” engineers laugh at the mention of metastability and almost do not believe it exists.
4) I do not know how to convenience a client of the detrimental impact of ignoring CDC issues and metastability when their own engineers do not believe that metastability exist. Moreover, there may be hundreds of unsynchronised paths in their source developed for the prototype.
