Universal FPGA Testing Methodology (UFTM™) is largely based on the principles of the world renowned, industry standard, Universal Verification Methodology (UVM). UVM is used and applied to functionally verify digital logic designs implemented using Hardware Description Languages (HDL) like VHDL, Verilog, System Verilog in simulation. UVM and UVM System Verilog class libraries are used in developing reusable and scalable System Verilog (High-level Verification Language (HVL)) verification testbenches or verification environments called Universal Verification Components (UVC). System Verilog for verification is an Object Oriented Software like subset of System Verilog language mainly used to implement testbenches for functional simulation verification of digital designs.
There has been a need for such a methodology for testing FPGA (Programmable Logic) design, FPGA design integration and FPGA based embedded system in hardware. Enter the UFTM. UFTM is the UVM equivalent answer to FPGA testing. UFTM is applied using and includes a base class library of Python Object Oriented Programming Language. UFTM supports the same capabilities that other verification languages support – from transaction level modelling, to functional coverage (under development) and randomised test generation, to data structures and to basic utilities. The intention of UFTM goes beyond capability though – UFTM intends to make FPGA testing environments, easy, readable, reusable (Vertical & Horizontal reusability) and scalable.
UFTM Essential Features
UFTM offers the similar capabilities as those based on System Verilog UVM.
- Transaction-Level Modeling
- Constrained Random test generation
- Functional Coverage (under development)
- Transcript files
- Error logging and reporting
- Message filtering – Logs
- Scoreboards and FIFOs (data structures for testing)
