I know that we would like to know how to capture activity in the implemented logic at reset time. The default simple trigger capture in Vivado Logic Analyzer is manual in which case it is impossible to capture such activity. However the following steps will enable you to add an automatic trigger at reset just after FPGA configuration is done. I quote the following steps from the Vivado Programming and Debugging UG908. Many times it becomes difficult to find such information especially when in need, therefore I have extracted here.
“Trigger At Startup
The Trigger at Startup feature is used to configure the trigger settings of an ILA core in a design .bit file so that it is pre-armed to trigger immediately after device startup. You do this by taking the various trigger settings that ordinarily get applied to an ILA core running in a design in hardware, and applying them to the ILA core in the implemented design.
IMPORTANT: The following process for using Trigger at Startup assumes that you are have a valid ILA design working in hardware, and that the ILA core has NOT been flattened during the synthesis flow.
To use the Trigger at Startup feature perform the following steps:
1. Run through the first pass of the ILA flow as usual to set up the trigger condition.
a. Open the target, configure the device, and bring up the ILA Dashboard.
b. Enter the trigger equations for the ILA core in the ILA Dashboard.
2. From the Vivado Tcl command line, export the trigger register map file for the ILA core. This file contains all of the register settings to “stamp” back on to the implemented netlist. The output from this is a single file.
% run_hw_ila -file ila_trig.tas [get_hw_ilas hw_ila_1]
3. Go back and open the previously implemented routed design in Vivado IDE. There are two ways to do this depending on your project flow.
a. Project Mode: Use the Flow Navigator to open the implemented design.
b. Non-Project Mode: Open your routed checkpoint:
% open_checkpoint <file>.dcp
4. At the Implemented Design Tcl console, apply the trigger settings to the current design in memory, which is your routed netlist.
% apply_hw_ila_trigger ila_trig.tas
Note: If you see an ERROR indicating that the ILA core has been flattened during synthesis, you will need to regenerate your design and force synthesis to preserve hierarchy for the ILA core. Ensure that you are have a valid ILA design working in hardware, and that the ILA core has NOT been flattened during the synthesis flow
5. At the Implemented Design Tcl console, write the bitstream with Trigger at Startup settings.
IMPORTANT: To pick up the routed design changes do this at the tcl command console only:
write_bitstream trig_at_startup.bit
6. Go back to the Hardware Manger and reconfigure with the new .bit file that you generated in the previous step. You will have to set the property for the updated .bit file location either through the GUI or through a Tcl command. Make sure you set the new .bit file as the one to use for configuration in the hardware tool.
a. Select the device in the hardware tree
b. Assign the .bit file generated in step 5
7. Program the device using the new .bit file. Once programmed, the new ILA core should immediately arm at startup. You should see an indication in the Trigger Capture Status for the ILA core. If trigger or capture events have occurred, the ILA core is now populated with captured data samples.”
