{"id":287,"date":"2025-07-07T17:51:35","date_gmt":"2025-07-07T16:51:35","guid":{"rendered":"https:\/\/blog.edgesmart.co.uk\/?p=287"},"modified":"2025-07-07T17:51:35","modified_gmt":"2025-07-07T16:51:35","slug":"amd-vivado-2025-1-adds-full-vhdl-code-coverage-free-mixed-language-coverage-driven-verification-just-got-real","status":"publish","type":"post","link":"https:\/\/blog.edgesmart.co.uk\/index.php\/2025\/07\/07\/amd-vivado-2025-1-adds-full-vhdl-code-coverage-free-mixed-language-coverage-driven-verification-just-got-real\/","title":{"rendered":"AMD Vivado\u2122 2025.1 Adds Full VHDL Code Coverage \u2014 Free Mixed-Language Coverage Driven Verification Just Got Real"},"content":{"rendered":"\n<p>The 2025.1 release of the <strong>Vivado\u2122 Design Suite: ML Standard Edition<\/strong> marks a quiet but significant milestone: <strong>VHDL code coverage support<\/strong> has been officially added to the simulator. This enhancement makes Vivado a fully capable, <strong>mixed-language, coverage-driven simulation platform<\/strong> \u2014 and it\u2019s still completely <strong>free<\/strong>.<\/p>\n\n\n\n<p>Until now, Vivado supported:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Verilog<\/strong> and <strong>SystemVerilog<\/strong> simulation<\/li>\n\n\n\n<li><strong>UVM testbench environments<\/strong><\/li>\n\n\n\n<li>Functional and structural coverage \u2014 <strong>but only for Verilog\/SystemVerilog<\/strong><\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">With the 2025.1 update, Vivado now supports:<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\"><strong>Code Coverage Support (VHDL, Verilog, SystemVerilog)<\/strong><\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Line Coverage<\/strong>: Tracks which lines of code have been executed.<\/li>\n\n\n\n<li><strong>Toggle Coverage<\/strong>: Monitors transitions (0\u21921 and 1\u21920) on nets and variables.<\/li>\n\n\n\n<li><strong>Condition Coverage<\/strong>: Observes Boolean sub-expressions inside conditions.<\/li>\n\n\n\n<li><strong>Branch\/Decision Coverage<\/strong>: Evaluates whether both the true and false branches of conditionals have been exercised.<\/li>\n<\/ul>\n\n\n\n<p>All of the above are now available for:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Pure VHDL<\/strong> designs<\/li>\n\n\n\n<li><strong>Pure Verilog\/SystemVerilog<\/strong><\/li>\n\n\n\n<li><strong>Mixed-language RTL<\/strong>, where VHDL and Verilog coexist<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\"><strong>Functional Coverage (SystemVerilog\/UVM)<\/strong><\/h3>\n\n\n\n<p>Vivado continues to support <strong>SystemVerilog functional coverage<\/strong> constructs, including:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Covergroups<\/strong><\/li>\n\n\n\n<li><strong>Coverpoints<\/strong><\/li>\n\n\n\n<li><strong>Cross coverage<\/strong><\/li>\n\n\n\n<li><strong>Bins and user-defined sampling<\/strong><\/li>\n<\/ul>\n\n\n\n<p>These constructs can be used in <strong>UVM<\/strong> testbenches \u2014 which are also supported in Vivado\u2019s simulator \u2014 making it a rare example of a <strong>free simulator with UVM + functional coverage<\/strong> support.<\/p>\n\n\n\n<p>While <strong>VHDL lacks native support for functional coverage constructs<\/strong>, you can now verify mixed-language designs by integrating a SystemVerilog UVM environment and collecting both functional and structural coverage metrics \u2014 all within Vivado.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Why This Matters<\/h3>\n\n\n\n<p>This update is not just incremental \u2014 it\u2019s strategic. AMD is now offering what traditionally required expensive tools from:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Synopsys (VCS)<\/strong><\/li>\n\n\n\n<li><strong>Cadence (Xcelium)<\/strong><\/li>\n\n\n\n<li><strong>Siemens EDA (Questa\/ModelSim)<\/strong><\/li>\n<\/ul>\n\n\n\n<p>\u2026 <em>for free<\/em>, with Vivado ML Standard Edition.<\/p>\n\n\n\n<p>Whether you&#8217;re:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>An <strong>academic researcher<\/strong><\/li>\n\n\n\n<li>A <strong>startup building on a budget<\/strong><\/li>\n\n\n\n<li>A <strong>consultant working with VHDL\/Verilog legacy IP<\/strong><\/li>\n\n\n\n<li>Or an <strong>FPGA engineer validating UVM testbenches<\/strong><\/li>\n<\/ul>\n\n\n\n<p>\u2026you now have access to <strong>industry-standard, coverage-driven, mixed-language verification<\/strong>, without license restrictions or costly toolchains.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Final Thoughts<\/h3>\n\n\n\n<p>Vivado 2025.1&#8217;s VHDL coverage support is a major leap for the open FPGA ecosystem. It&#8217;s a clear signal that <strong>verification is no longer a premium feature<\/strong> \u2014 it&#8217;s a necessity, and now it\u2019s accessible to all.<\/p>\n\n\n\n<p><strong>I think AMD has just raised the bar for what a free EDA tool can and should offer.<\/strong><\/p>\n\n\n\n<p>#Vivado #FPGA #VHDL #SystemVerilog #Verilog #RTLDesign #UVM #EDA #CodeCoverage #FunctionalCoverage #Simulation #MixedLanguage #FreeTool #Verification #DesignVerification #ASIC #VLSI #FPGAVerification #OpenEDA #Vivado2025<\/p>\n","protected":false},"excerpt":{"rendered":"<p>The 2025.1 release of the Vivado\u2122 Design Suite: ML Standard Edition marks a quiet but significant milestone: VHDL code coverage support has been officially added to the simulator. This enhancement makes Vivado a fully capable, mixed-language, coverage-driven simulation platform \u2014 and it\u2019s still completely free. Until now, Vivado supported: With the 2025.1 update, Vivado now &hellip;<br \/><a href=\"https:\/\/blog.edgesmart.co.uk\/index.php\/2025\/07\/07\/amd-vivado-2025-1-adds-full-vhdl-code-coverage-free-mixed-language-coverage-driven-verification-just-got-real\/\" class=\"more-link pen_button pen_element_default pen_icon_arrow_double\">Continue reading <span class=\"screen-reader-text\">AMD Vivado\u2122 2025.1 Adds Full VHDL Code Coverage \u2014 Free Mixed-Language Coverage Driven Verification Just Got Real<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-287","post","type-post","status-publish","format-standard","hentry","category-uncategorised"],"_links":{"self":[{"href":"https:\/\/blog.edgesmart.co.uk\/index.php\/wp-json\/wp\/v2\/posts\/287","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blog.edgesmart.co.uk\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blog.edgesmart.co.uk\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blog.edgesmart.co.uk\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.edgesmart.co.uk\/index.php\/wp-json\/wp\/v2\/comments?post=287"}],"version-history":[{"count":1,"href":"https:\/\/blog.edgesmart.co.uk\/index.php\/wp-json\/wp\/v2\/posts\/287\/revisions"}],"predecessor-version":[{"id":288,"href":"https:\/\/blog.edgesmart.co.uk\/index.php\/wp-json\/wp\/v2\/posts\/287\/revisions\/288"}],"wp:attachment":[{"href":"https:\/\/blog.edgesmart.co.uk\/index.php\/wp-json\/wp\/v2\/media?parent=287"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blog.edgesmart.co.uk\/index.php\/wp-json\/wp\/v2\/categories?post=287"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blog.edgesmart.co.uk\/index.php\/wp-json\/wp\/v2\/tags?post=287"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}