The 2025.1 release of the Vivado™ Design Suite: ML Standard Edition marks a quiet but significant milestone: VHDL code coverage support has been officially added to the simulator. This enhancement makes Vivado a fully capable, mixed-language, coverage-driven simulation platform — and it’s still completely free.
Until now, Vivado supported:
- Verilog and SystemVerilog simulation
- UVM testbench environments
- Functional and structural coverage — but only for Verilog/SystemVerilog
With the 2025.1 update, Vivado now supports:
Code Coverage Support (VHDL, Verilog, SystemVerilog)
- Line Coverage: Tracks which lines of code have been executed.
- Toggle Coverage: Monitors transitions (0→1 and 1→0) on nets and variables.
- Condition Coverage: Observes Boolean sub-expressions inside conditions.
- Branch/Decision Coverage: Evaluates whether both the true and false branches of conditionals have been exercised.
All of the above are now available for:
- Pure VHDL designs
- Pure Verilog/SystemVerilog
- Mixed-language RTL, where VHDL and Verilog coexist
Functional Coverage (SystemVerilog/UVM)
Vivado continues to support SystemVerilog functional coverage constructs, including:
- Covergroups
- Coverpoints
- Cross coverage
- Bins and user-defined sampling
These constructs can be used in UVM testbenches — which are also supported in Vivado’s simulator — making it a rare example of a free simulator with UVM + functional coverage support.
While VHDL lacks native support for functional coverage constructs, you can now verify mixed-language designs by integrating a SystemVerilog UVM environment and collecting both functional and structural coverage metrics — all within Vivado.
Why This Matters
This update is not just incremental — it’s strategic. AMD is now offering what traditionally required expensive tools from:
- Synopsys (VCS)
- Cadence (Xcelium)
- Siemens EDA (Questa/ModelSim)
… for free, with Vivado ML Standard Edition.
Whether you’re:
- An academic researcher
- A startup building on a budget
- A consultant working with VHDL/Verilog legacy IP
- Or an FPGA engineer validating UVM testbenches
…you now have access to industry-standard, coverage-driven, mixed-language verification, without license restrictions or costly toolchains.
Final Thoughts
Vivado 2025.1’s VHDL coverage support is a major leap for the open FPGA ecosystem. It’s a clear signal that verification is no longer a premium feature — it’s a necessity, and now it’s accessible to all.
I think AMD has just raised the bar for what a free EDA tool can and should offer.
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